The present invention relates to a bus system employed in information processing apparatuses such as a workstation, a personal computer, and a word processor.
The bus system disposed in the information processing apparatus is configured; like a bus system described in a report “EISA” written by L. Brett Glass in pages 417 to 424 of “BYTE”, Volume 14, Number 12 (1989); such that memory and system buses are respectively connected to a processor bus or processor and memory buses are respectively linked to the system bus.
In the former constitution, during a cooperative action of the system and memory buses, namely, during the so-called direct memory access (DMA), the processor bus cannot operate in an independent fashion, which consequently leads to a deterioration of the utilization efficiency of the processor bus. In the latter case, on the other hand, during a cooperative operation of the processor and memory buses i.e. during the so-called main memory access, the system bus cannot operate in an independent manner, thereby leading to a problem of a deterioration of the utilization efficiency of the system bus.
In this regard, the configuration and the problems of the conventional bus system will be described in detail later by referring to drawings.